PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 220

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

After transmission is complete, the optional generation of the ALLS interrupt indicates
that all transmit data has been sent on pin TxD.
Note: In HDLC Automode, the ’XF’ command may be replaced by the ’XIF’ command in
Figure 55
Data Sheet
Packet n:
Packet (n+1):
End (TDTE) interrupt is generated whenever a block of <XBC> bytes is completely
transferred. For the last buffer, containing the end of the transmit packet, the ’XF’
command is issued together with bit ’XME’ set (refer to
(write transmit byte count with command
the same register, when transmission of an I-frame is desired.
(prepare external DMA controller
(prepare external DMA controller
DMA Transmit (Single Buffer per Packet)
(write transmit byte count with
<XBC> transmit data
with buffer base address)
with buffer base address)
command bit 'XF'+'XME')
ALLS interrupt (optional)
DMA transfer of
CPU / MEMORY
TDTE interrupt
bit 'XF'+'XME')
bytes
220
...
...
SEROCCO-H
XBC
TFIFO
TFIFO
TFIFO
XBC
Figure
56).
Programming
PEB 20525
PEF 20525
2000-09-14