PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 29

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Table 1
Pin No.
P-
LFBGA-
80-2
J5
J6
Data Sheet
P-TQFP-
100-3
39
42
Microprocessor Bus Interface
Symbol In (I)
A0
BLE
UDS
BM
ALE
Out (O)
I
I
I
I
I
Function
Address Line A0 (8-bit modes)
In Motorola and in Intel 8-bit mode this signal
represents the least significant address line.
Byte Low Enable (16-bit Intel bus mode)
This signal indicates a data transfer on the lower
byte of the data bus (D7..D0). Together with
signal BHE the type of bus access is determined
(byte or word access at even or odd address).
Upper Data Strobe (16-bit Motorola bus mode)
This active low strobe signal serves to control
read/write operations. Together with signal LDS
the type of bus access is determined.
Bus Mode
– BM = static ’1’ for operation in Motorola bus
– BM = static ’0’ for operation in Intel bus mode
– Pin BM/ALE has the function of an Address
Address Latch Enable (mux’ed Intel bus)
The address is latched by the SEROCCO-H with
the falling edge of ALE.
The address input pins A(7:0) pins A(15:0) must
be externally connected to the data bus pins
D(7:0)D(15:0).
For operation of the 8-bit SEROCCO-H (P-
LFBGA-80-2 package) in a 16-bit environment,
A(7:0) should be connected to address/data lines
AD(8:1) of the external bus. D(7:0) interface to
AD(7:0) of the external bus.
mode (de-multiplexed).
with de-multiplexed address and data buses.
Latch Enable (ALE) for operation in Intel bus
mode with a multiplexed address/data bus. A
falling edge on this pin selects Intel multiplexed
bus mode.
29
Pin Descriptions
PEB 20525
PEF 20525
2000-09-14