PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 155

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Data Sheet
RAC
ESS7
DRCRC
RCRC
Receiver active
Switches the receiver between operational/inoperational states:
RAC=’0’
RAC=’1’
Enable SS7 Mode
This bit is only valid in HDLC mode only.
ESS7=’0’
ESS7=’1’
Note: If SS7 mode is enabled, ’Address Mode 0’ must be selected by
Disable Receive CRC Checking
DRCRC=’0’
DRCRC=’1’
Receive CRC Checking Mode
RCRC=’0’
RCRC=’1’
setting bit field CCR2L:MDS(1:0) to ’10’ and bit CCR2L:ADM to ’0’.
Receiver inactive, receive line is ignored.
Receiver active.
Disable signaling system #7 (SS7) support.
Enable signaling system #7 (SS7) support.
The receiver expects a 16 or 32 bit CRC within a HDLC
frame. CRC processing depends on the setting of bit
’RCRC’.
Frames shorter than expected are marked ’invalid’ or are
discarded (refer to
The receiver does not expect any CRC within a HDLC
frame. The criteria for ’valid frame’ indication is updated
accordingly (refer to
Bit ’RCRC’ is ignored.
The received checksum is evaluated, but NOT forwarded
to the receive FIFO.
The received checksum (2 or 4 bytes) is evaluated and
forwarded to the receive FIFO as data.
5-155
RSTA
RSTA
Register Description (CCR3H)
description).
description).
PEB 20525
PEF 20525
2000-09-14