PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 18

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

• Bit Synchronous PPP Mode
• Octet Synchronous PPP Mode
• Extended Transparent Mode
• Protocol and Mode Independent
Protocol Support
• Address Recognition Modes
• HDLC Automode
• Signaling System #7 (SS7) support
• Optional DTACK/READY controlled cycles
Data Sheet
– CRC generation and checking (CRC-CCITT or CRC-32)
– Transparent CRC option per channel and/or per frame
– Programmable Preamble (8 bit) with selectable repetition rate
– Error detection (abort, long frame, CRC error, short frames)
– Bit oriented transmission of HDLC frame (flag, data, CRC, flag)
– Zero bit insertion/deletion
– 15 consecutive ’1’ bits abort sequence
– Octet oriented transmission of HDLC frame (flag, data, CRC, flag)
– Programmable character map of 32 hard-wired characters (00
– Four programmable characters for additional mapping
– Insertion/deletion of control-escape character (7D
– Fully bit transparent (no framing, no bit manipulation)
– Octet-aligned transmission and reception
– Data bit inversion
– Data overflow and underrun detection
– Timer
– No address recognition (Address Mode 0)
– 8-bit (high byte) address recognition (Address Mode 1)
– 8-bit (low byte) or 16-bit (high and low byte) address recognition (Address Mode 2)
– 8-bit or 16-bit address generation/recognition
– Support of LAPB/LAPD
– Automatic handling of S- and I-frames
– Automatic processing of control byte(s)
– Modulo-8 or modulo-128 operation
– Programmable time-out and retry conditions
– SDLC Normal Response Mode (NRM) operation for slave
– Detection of FISUs, MSUs and LSSUs
– Unchanged Fill-In Signaling Units (FISUs) not forwarded
– Automatic generation of FISUs in transmit direction (incl. sequence number)
– Counting of errored signaling units
18
H
) for mapped characters
H
-1F
H
)
Introduction
PEB 20525
PEF 20525
2000-09-14