PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 31

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PEF 20525 F V1.3

Manufacturer Part Number
PEF 20525 F V1.3
Description
IC CTRL PPP/HDLC SERIAL TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20525 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20525FV1.3X
PEF20525FV13XP
SP000007592
Table 1
Pin No.
P-
LFBGA-
80-2
G8
-
G7
H1
Data Sheet
P-TQFP-
100-3
53
33
55
20
Microprocessor Bus Interface
Symbol In (I)
WR
WIDTH
CLK
INT/INT O
Out (O)
I
I
I
o/d
Function
Write Strobe (Intel bus mode only)
This signal indicates a write operation. The
current bus master presents valid data on lines
D(7:0) / D(15:0) during an active WR signal.
In Motorola bus mode, a pull-up resistor to V
recommended on this pin.
Width Of Bus Interface
A low signal on this input selects the 8-bit bus
interface mode.
A high signal on this input selects the 16-bit bus
interface mode. In this case word transfer to/from
the internal registers is enabled. Byte transfers
are implemented by using BLE and BHE (Intel bus
mode) or LDS and UDS (Motorola bus mode)
In P-LFBGA-80-2 package this signal is not
available, since only 8 bit bus width is supported.
Clock
The system clock for SEROCCO-H is provided
through this pin.
Interrupt Request
The INT/INT goes active when one or more of the
bits in registers
to these registers clears the interrupt. The INT/
INT line is inactive when all interrupt status bits
are reset.
Interrupt sources can be unmasked in registers
IMR0..IMR2
’0’.
31
by setting the corresponding bits to
ISR0..ISR2
are set to ’1’. A read
Pin Descriptions
PEB 20525
PEF 20525
2000-09-14
DD3
is

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