peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 10

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

List of Figures
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Data Sheet
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
General System Integration (PCI Bus Interface) . . . . . . . . . . . . . . . . . 24
General System Integration (De-multiplexed Interface) . . . . . . . . . . . . 25
HSSI Application - DCE Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
HSSI Application - DTE Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
General Data Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DSCC4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Master Single READ Transaction followed by a Master
Single WRITE Transaction in De-multiplexed Configuration . . . . . . . . 54
Master Burst WRITE/READ Transaction in
De-multiplexed Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DMA Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Transmit Descriptor List Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Transmit Descriptor Memory Example. . . . . . . . . . . . . . . . . . . . . . . . . 70
Receive Descriptor List Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Receive Descriptor Memory Example . . . . . . . . . . . . . . . . . . . . . . . . . 75
Data Transfer controlled via first and last descriptor addresses . . . . . 78
Example: ’Chain Jump’ Handling per ’Dummy Descriptor’. . . . . . . . . . 80
DSCC4 Logical Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Central Transmit FIFO Section Thresholds . . . . . . . . . . . . . . . . . . . . . 90
Central Receive FIFO Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Little/Big Endian Byte Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
MFP Configurations Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Multiplexed Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
De-multiplexed Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Memory Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LRDY Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LRDY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
External Bus Arbitration (Releasing the Bus). . . . . . . . . . . . . . . . . . . 108
External Bus Arbitration (Regaining the Bus) . . . . . . . . . . . . . . . . . . 109
Connection of the Master and Slave Bus Arbitration Signals . . . . . . 110
Bus Arbitration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Registers and Port Pins associated with the SSC . . . . . . . . . . . . . . . 116
Synchronous Serial Channel SSC Block Diagram. . . . . . . . . . . . . . . 117
Serial Clock Phase and Polarity Options . . . . . . . . . . . . . . . . . . . . . . 119
SSC Full Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SSC Half Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SSC Error Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10
PEB 20534
PEF 20534
2000-05-30
Page