peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 50

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

PEB 20534
PEF 20534
Functional Description
General Data Flow Description
For register read/write transaction, each single block can be accessed by the host CPU
via the PCI (or de-multiplexed) bus interface.
The DSCC4 central TFIFO and RFIFO provide space for 128 DWORDs each to be
shared by four serial channels (4 SCCs).
Four DMA Controller Channels (DMACs) transfer data associated with the serial
channels from shared memory via the PCI interface into the central TFIFO. These data
are forwarded from the TFIFO to the four SCCs.
In receive direction the serial channels (4 SCCs) deliver received data into the central
RFIFO. Another four DMACs transfer these data from the central RFIFO via the PCI
interface into shared memory locations, associated with the serial ports.
The SCCs as well as the peripheral blocks (LBI, GPP, SSC) are able to generate
interrupts. Corresponding interrupt vectors are delivered by any single block the central
interrupt controller and its 16 DWORDs interrupt queue. A DMAC transfers the interrupt
vectors from the interrupt queue into appropriate locations in the shared memory.
Data and interrupt buffering exists in each block as its interface is contending for the
internal busses. The access to the internal busses is controlled by arbiters that are not
shown in the block diagram.
Data Sheet
50
2000-05-30