peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 134

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

7.3.2
The SCC receive FIFO is divided into two parts of 15 and 2 DWORDs. The interface
between the two parts provides clock synchronization between the system clock domain
and the protocol logic working with the serial receive clock.
Figure 40
With standard register settings (i.e. the SCC receive FIFO threshold is not reduced, refer
to
receive FIFO requests data transfer to the central RFIFO if the 15 DWORDs part is
completely filled or a frame end / block end condition is detected.
This SCC receive FIFO size is optimized for high speed channel configurations. The 15
DWORDs FIFO part is transferred to the central RFIFO allocating one consecutive block
of RFIFO memory. This guarantees full 15 DWORDs burst length on the PCI/De-
multiplexed system interface which can be performed on consecutive RFIFO sections
only (refer to
Nevertheless this FIFO depth might cause too long delay in low speed channel
configurations on data transfer to the host memory (especially ASYNC/BISYNC protocol
modes). Therefore the SCC receive FIFO threshold can be lowered in some steps
downto 1 data byte causing the SCC to request data transfer to the central RFIFO as
soon as this threshold is reached. The threshold is adjusted by bit field ’RFTH’ in register
CCR2.
In addition data stored in the SCC receive FIFO can be transferred to the central RFIFO
any time on request by setting command ’RFRD’ in register CMDR. Prior to issuing a
’RFRD’ command, the "receive FIFO not empty condition" can be tested by the host CPU
by reading bit ’RFNE’ in register STAR.
Furthermore in ASYNC mode this ’RFRD’ command can be generated automatically on
a time out condition if enabled via bit ’TOIE’ in register CCR1. In ASYNC applications
characters are often send in blocks which means a small time gap between characters
of these blocks; but also single control characters may be interleaved. In this case the
receive FIFO threshold might be adjusted to the length of expected ASYNC character
Data Sheet
Table 69 "CCR2: Channel Configuration Register 2" on Page
to central
RFIFO
SCC Receive FIFO
Chapter
SCC Receive FIFO
5.2.3, "
Central Receive FIFO
Serial Communication Controller (SCC) Cores
system clock
134
domain
(RFIFO)").
receive clock
domain
from serial
line and protocol
logic
296), the SCC
PEB 20534
PEF 20534
2000-05-30