peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 89

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

5.2.2
The central transmit FIFO can be partitioned in 4 sections with 128 DWORDs in total.
Each section size can be programmed according to the needs of the corresponding
serial port via register FIFOCR1. Criteria for partitioning are serial line speed (nominal
data rate) and type of traffic (bursty or constant). The software has to ensure that the sum
of section sizes does not exceed the 128 DWORDs total limit. One channel can consume
only 124 DWORDs of the central transmit FIFO.
Two thresholds per TFIFO section are provided to optimize TFIFO operation to the serial
side as well as the system interface side.
These thresholds have conflicting requirements:
1. Minimizing transmit data underrun probability in case of PCI bus latencies (especially
2. Reducing bus utilization by making maximum PCI burst transfers possible for loading
As a naming convention Transmit FIFO always means the Transmit FIFO section of the
dedicated channel. All considerations apply to one transmit channel.
Requirement 1) is controlled by the Transmit FIFO forward threshold (register
FIFOCR4). Transmit data is transferred to its SCC if one of the following conditions is
true:
• A complete packet is stored in the TFIFO (Frame End (FE) indication detected). In this
• The TFIFO is filled beyond the forward threshold.
These two conditions are checked again after every transfer of a complete frame to the
SCC.
Consider a small frame is stored in the transmit FIFO and the beginning of a second
frame, but the total amount of data is smaller than the forward threshold (DMAC
operation may be delayed by bus latency now). The TFIFO will start transferring data to
the SCC because a frame end (FE) indication is detected. After transfer of the complete
first frame the above two conditions are checked again. Now there is no further FE
indication in the TFIFO and the forward threshold is not exceeded. Thus the TFIFO will
not start transferring the second frame until additional data is loaded.
Requirement 2) is controlled by the Transmit FIFO refill threshold (register FIFOCR2). In
case of an empty transmit FIFO the DMAC always tries to fill the complete TFIFO with
data. If a TFIFO full condition occurs, the DMAC gets stopped. The DMAC starts again
if the TFIFO fill level falls below the refill threshold and tries to get new data via the PCI
bus until the TFIFO is filled again.
Data Sheet
for high speed ports).
of transmit data.
case data transfer to the SCC will start although the frame is smaller than the forward
watermark.
Central Transmit FIFO (TFIFO)
89
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
2000-05-30