peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 299

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
DPS
DRCRC
RCRC
RADD
Data Parity Storage
Only valid if parity generation/checking is enabled via bit ’PARE’:
DPS=’0’
DPS=’1’
Disable Receive CRC Checking
DRCRC=’0’
DRCRC=’1’
Receive CRC Checking Mode
This bit is only valid in Non-Automode and Address Mode 0:
RCRC=’0’
RCRC=’1’
Receive Address Pushed to RFIFO
This bit is only valid if a HDLC sub-mode with address field support is
selected (Automode, Non-Automode, Address Mode 1):
RADD=’0’
RADD=’1’
The parity bit is stored.
The parity bit is not stored in the data byte containing
character data.
The parity bit is always stored in the status byte.
The receiver expects a 16 or 32 bit CRC within a HDLC
frame. CRC processing depends on the setting of bit
’RCRC’.
Frames shorter than expected are marked ’invalid’ or are
discarded (refer to RSTA description).
The receiver does not expect any CRC within a HDLC
frame. The criteria for ’valid frame’ indication is updated
accordingly (refer to RSTA description).
Bit ’RCRC’ is ignored.
The received checksum is evaluated, but not forwarded to
the receive FIFO.
The received checksum (2 or 4 bytes) is evaluated and
forwarded to the receive FIFO as data. In Non-Automode
the criteria for ’valid frame’ is updated (refer to RSTA
description).
The received HDLC address field (either 8 or 16 bit
depending on bit ’ADM’) is evaluated, but NOT forwarded
to the receive FIFO.
The received HDLC address field (either 8 or 16 bit
depending on bit ’ADM’) is evaluated and forwarded to the
receive FIFO.
299
Detailed Register Description
(async/bisync modes)
PEB 20534
PEF 20534
(hdlc mode)
(hdlc mode)
(hdlc mode)
2000-05-30