peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 235

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
CFGIQP
TXPRi
(i=3...0)
Configure Interrupt Queue Peripheral
Only valid, if action request bit ’AR’ is set.
The DSCC4 DMA (interrupt) controller will transfer interrupt vectors
generated by the Local Bus Interface (LBI) to the peripheral interrupt
queue which must be configured via ’CFGIQP’ command bits:
bit=’0’
bit=’1’
Transmit Poll Request Channel i
Self-clearing command bit, only valid in ’HOLD’ bit controlled DMA
controller mode (bit CMODE = ’0’ in register GMODE):
TXPRi=’0’
TXPRi=’1’
The DSCC4 DMA (interrupt) controller does NOT
configure/re-configure the peripheral interrupt queue, if
action request bit ’AR’ is set to ’1’.
Causes the DSCC4 DMA (interrupt) controller to configure
the peripheral interrupt queue, if action request bit ’AR’ is
set to ’1’.
On action request, the DMA (interrupt) controller will
evaluate the peripheral interrupt queue base address and
length registers which must have been programmed by
software before.
No Transmit Poll Request is performed. The
corresponding DMA controller transmit channel is
stopped when HOLD=’1’ has been detected in the current
transmit descriptor.
Setting this bit to ’1’, when HOLD=’1’ has been detected
in the current transmit descriptor, will cause the DSCC4 to
poll the ’HOLD’ bit in the current transmit descriptor, i.e.
the DSCC4 reads the configuration word (DWORD 0) and
next descriptor address (DWORD 1) of the current
descriptor again. If the ’HOLD’ bit is detected cleared (’0’),
the DMA controller will branch to the next descriptor.
When the DMA controller is not in ’HOLD’ state, this
command is discarded.
235
Detailed Register Description
(Channel TX 3...0)
PEB 20534
PEF 20534
2000-05-30
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