peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 253

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 52
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
Bit 31
Bit 15
IQPBAR
30
14
IQPBAR:
Interrupt Queue Peripheral Base Address Register
This register determins the base address of the peripheral interrupt
queue and can be located anywhere in the 32 bit address range.
Note: The interrupt queue base address must be 32-bit aligned, i.e. bit 1
29
13
28
12
and 0 must be set to ’0’.
read/write
0000 0000
0040
written by CPU
evaluated by DSCC4
27
11
H
26
10
H
IQPBAR(15:2)
25
9
IQPBAR(31:16)
24
253
8
23
7
22
6
Detailed Register Description
21
5
20
4
19
3
18
2
PEB 20534
PEF 20534
2000-05-30
17
1
0
16
0
0
(-)