peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 93

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

5.2.4
System Interface Arbitration (DMA Arbiter):
Once the DMA controller has been granted PCI bus access, it will attempt to transfer all
of its available data in one bus access. However the PCI access time is limited by the
PCI bus protocol (bus arbitration and latency timer operation).
There are three priority groups as defined below:
Within each group, the group priority is shared between the channels by the round robbin
rules. After each bus access the priority is re-computed for the next access based on the
round robbin rules. The DMA arbiter steps through three groups of priority in case of at
least one DMA request per group is pending.
Priority groupings:
1. The DMA channel performing the interrupt vector transfer has the highest (first)
2. The DMA channels performing the data transfer in receive direction have the second
3. The DMA channels performing the data transfer in transmit direction have the third
The sub-priority of the DMA channels within the receiver or transmitter group is the same
or one channel is treated as ’high priority channel’.
This exclusive priority can be enabled via bit ’SPRI’ in register GMODE whereas the
dedicated channel can be selected via bit field ’PCH’ in register GMODE. This setting
also effects the internal SCC arbitration.
Internal SCC Arbitration (SCC Arbiter):
Two independent arbiters control the service of the 4 SCC transmit and the 4 SCC
receive channels. Each arbiter either works following the round robbin scheme or
provides ’high priority’ to one dedicated channel and services the remaining channels in
a second priority group using round robbin.
This exclusive priority can be enabled via bit ’SPRI’ in register GMODE whereas the
dedicated channel can be selected via bit field ’PCH’ in register GMODE.
The high priority option is useful if one SCC is configured in high speed mode (up to
52 MBit/s) and the others are operating at slow data rates below 10 or 2 MBit/s. In this
case data transfer from and to the corresponding SCC FIFOs as well as data transfer
from and to host memory is preferred for the high speed transmit/receive channels. In all
other cases ’round robbin’ within the described priority groups provide a balanced
arbitration solution.
Data Sheet
priority to prevent over-runs and loss of interrupt vectors.
priority (receiver group).
priority (transmitter group).
DMAC Internal Arbitration Scheme
93
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
2000-05-30