peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 337

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
TIC
Transmit Immediate Character
On write access to this register the ASYNC protocol engine will
automatically insert the character defined by bit field ’TIC’ into the
transmit data stream.
This happens
• immediately after write access to register TICR if the transmitter is in
• immediately after the character which is currently in transmission is
The TIC transmission is independent off in-band flow control. Thus the
TIC is send out even if the transmitter is in XOFF-state. However the
transmitter must be enabled via signal CTS (depending on bit ’FCTS’ in
register CCR1).
The number of significant bits (starting with the LSB) depends on the
character length programmed in bit field ’CHL’ in register CCR2. All
character framing related settings in register CCR2 (start bit, parity
generation, number of stop bits) also apply to the TIC character framing.
As long as the TIC character is not completely send, status bit TIC
Execution (’TEC’) in status register STAR is set to ’1’ by the DSCC4. No
further write access to register TICR is allowed until ’TEC’ status
indication is cleared by the DSCC4.
IDLE state (no other character is currently transmitted). The
transmitter returns to IDLE state after transmission of the TIC.
completed. After transmission of the TIC, the transmitter continues
with transmission of characters which are still stored in the transmit
FIFO. Thus the TIC is inserted into the data stream between the
characters provided via the transmit FIFO.
337
Detailed Register Description
(async mode)
PEB 20534
PEF 20534
2000-05-30