peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 124

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Port Control:
The SSC uses three pins to communicate with the external world. Pin MCLK serves as
the clock line, while pins MRST (Master Receive/Slave Transmit) and MTSR (Master
Transmit/Slave Receive) serve as the serial data input/output lines. The operation of
these pins depends on the selected operating mode (master or slave).
The direction of the port lines depends on the operating mode, that is selected via
SSCCON:SSCMS.
6.2.1.4
The SSC interface has its own dedicated 16-bit baud rate generator with 16-bit reload
capability, allowing baud rate generation independent from timers.
The baud rate generator is clocked with the CPU clock divided by 2 (10 MHz @ 20 MHz
bus clock). The timer is counting downwards and can be started or stopped through the
global enable bit SSCEN in the SSC Control register SSCCON.
The register SSCCON (refer to section
the dual-function Baud Rate Generation register. Reading SSCBR, while the SSC is
enabled, returns the contents of the timer. Reading SSCBR, while the SSC is disabled,
returns the programmed reload value. In this mode the desired reload value can be
written to SSCBR.
The formulas below calculate either the resulting baud rate for a given reload value, or
the required reload value for a given baudrate:
Bit field <SSCBR> represents the contents of the reload register, taken as an unsigned
16-bit integer.
The maximum baud rate that can be achieved when using a PCI clock of 20 MHz is 5
MBaud. The table below lists some possible baud rates together with the required reload
values and the resulting bit times, assuming a PCI clock of 20 MHz. A PCI clock of
33 MHz is also supported.
6.2.1.5
The SSC is able to detect four different error conditions. Receive Error and Phase Error
are detected in all modes, while Transmit Error and Baudrate Error only apply to slave
mode. When an error is detected, the respective error flag is set. When the
corresponding error enable bit is set, also an error interrupt request will be generated by
setting SSCERI (see
flags to determine the cause of the error interrupt. The error flags are not reset
Data Sheet
Baudrate
SSC
Baud Rate Generation
Error Detection
=
2 * (<SSCBR> + 1)
Figure
f
CPU
38). The error interrupt handler may then check the error
“SSC Registers Description” on Page
124
SSCBR = (
2 * Baudrate
Multi Function Port (MFP)
f
CPU
SSC
PEB 20534
PEF 20534
) - 1
2000-05-30
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