peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 343

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
ALLS
XDU
ALL Sent Interrupt
HDLC Mode:
This bit is set to ’1’:
• if the last bit of the current HDLC frame is sent out via pin TxD,
• if an I-frame is sent out completely via pin TxD and either a valid
ASYNC/BISYNC Mode:
This bit is set to ’1’, if the last character is completely sent via pin TxD
and no further data is stored in the SCC transmit FIFO, i.e. the transmit
FIFO is empty.
Transmit Data Underrun Interrupt
HDLC Mode:
This bit is set to ’1’, if the current frame was terminated by the SCC with
an abort sequence, because neither a ’frame end / block end’ indication
was detected in the FIFO (to complete the current frame) nor more data
is available in the SCC transmit FIFO.
Note: The transmitter is stopped if this condition occurs and needs to be
BISYNC Mode:
This bit is set to ’1’, if the current transmission was terminated with IDLE
sequence because no more data is available in the SCC transmit FIFO.
Note: The transmitter is stopped if this condition occurs and needs to be
acknowledge S-frame has been received or a time-out condition
occured because no valid acknowledge S-frame has been received in
time (Automode).
reset via command bit ’XRES’ in register CMDR. Furthermore the
XDU interrupt indication MUST be cleared by generating an
interrupt vector, thus bit ’XDU’ should not be masked via register
IMR.
reset via command bit ’XRES’ in register CMDR. Furthermore the
XDU interrupt indication MUST be cleared by generating an
interrupt vector, thus bit ’XDU’ should not be masked via register
IMR.
343
Detailed Register Description
(hdlc/bisync mode)
PEB 20534
PEF 20534
(all modes)
2000-05-30