peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 99

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

6.1.1
6.1.1.1
The External Bus Controller (EBC) provides a flexible bus interface to connect a wide
range of peripherals. In normal mode this interface is a bus master (and default bus
owner) and drives peripheral devices. It provides the ability to select busses of different
configuration: 8 bit multiplexed/de-multiplexed or 16 bit multiplexed/de-multiplexed. The
configurable pins of address signals/general purpose signals provide alternate
functionality to support the LBI pins with additional I/O signals.
The EBC also supports bus arbitration supporting other bus masters connected to the
local bus. In this case, the DSCC4 can be configured as arbitration master (default bus
owner) or arbitration slave
The function of the EBC is controlled via the global mode register GMODE and the LBI
Configuration register LCONF. It specifies the external bus cycles in terms of address
(multiplexed/de-multiplexed), data (16-bit/8-bit) and control signal length (wait states).
6.1.1.2
In the 16-bit multiplexed bus mode both the address and data lines use the pins
LD(15:0). The address is time-multiplexed with the data and has to be latched externally.
The width of the required latch depends on the selected data bus width, i.e. an 8-bit data
bus requires an 8-bit latch (the address bits LD15...LD8 on the LBI port do not change,
while on LD7...LD0 address and data signals are multiplexed), a 16-bit data bus requires
a 16-bit latch (the least significant address line LA0 is not relevant for word accesses).
In de-multiplexed mode, the address lines are permanently output on pins LA(15:0) and
do not require latches.
The EBC initiates an external access by generating the Address Latch Enable signal
(LALE) and then placing an address on the bus. The falling edge of LALE triggers an
external latch to capture the address. After a period of time in which the address must
have been latched externally, the address is removed from the bus. The EBC now
activates the respective command signal (LRD, LWR, LRDY) and data is driven onto the
bus either by the EBC (for write cycles) or by the external memory/peripheral (for read
cycles). After a period of time, which is determined by the access time of the memory/
peripheral, data becomes valid.
Read cycles: Input data is latched and the command signal is now deactivated. This
causes the accessed device to remove its data from the bus which is then tri-stated
again.
Write cycles: The command signal is now deactivated. The data remain valid on the bus
until the next external bus cycle is started.
Data Sheet
LBI Bus Modes
LBI External Bus Controller (EBC)
Multiplexed Local Bus Modes
99
Multi Function Port (MFP)
PEB 20534
PEF 20534
2000-05-30