peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 191

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

8.2
8.2.1
Character framing is achieved by start and stop bits. Each data character is preceded by
one Start bit and terminated by one or two stop bits. The character length is selectable
from 5 up to 8 bits. Optionally, a parity bit can be added which complements the number
of ones to an even or odd quantity (even/odd parity). The parity bit can also be
programmed to have a fixed value (Mark or Space). The character format configuration
is performed via appropriate bit fields in register CCR2. Figure 71 shows the
asynchronous character format.
Figure 71
8.2.2
The SCC offers the flexibility to combine clock modes, data encoding and data sampling
in many different ways. However, only definite combinations make sense and are
recommended for correct operation:
8.2.2.1
Prerequisites:
• Bit clock rate 16 selected (register CCR0, bit BCR = ‘1’)
• Clock mode 0, 1, 3b, 4, or 7b selected (register CCR0, bit field ’CM’)
• NRZ data encoding selected (register CCR0, bit field ’SC’)
The receiver which operates with a clock rate equal to 16 times the nominal (expected)
data bit rate, synchronizes itself to each character by detecting and verifying the start bit.
Since character length, parity and stop bit length is known, the ensuing valid bits are
Data Sheet
1
Start
Bit
Asynchronous (ASYNC) Protocol Mode
Character Framing
Data Reception
Asynchronous Mode
Asynchronous Character Frame
(LSB)
D0
5 to 8 Data Bits
(6 to 9 Bits with Parity)
D1
D2
D3
Character Frame
D4
191
D5
Par.
D6
Par.
Detailed Protocol Description
D7
Par.
Parity
1 or 2
Stop
Bits
PEB 20534
PEF 20534
2000-05-30
ITD01804