peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 34

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin No.
9
31
33
Data Sheet
Symbol
IDSEL
DEVSEL
PERR
PCI Bus Interface(DEMUX Interface) (cont’d)
Input (I)
Output (O)
I
s/t/s
s/t/s
Function
Initialization Device Select
When DSCC4 is slave in a transaction and if
IDSEL is active in the address phase and C/
BE(3:0) indicates an config read or write
command, the DSCC4 assumes a read or
write to a configuration space register. In
response, the DSCC4 asserts DEVSEL during
the subsequent CLK cycle.
IDSEL is sampled on the rising edge of CLK.
Note: In DEMUX mode IDSEL is a chipselect
Device Select
When activated by a slave, it indicates to the
current bus master that the slave has decoded
its address as the target of the current
transaction. If no bus slave activates DEVSEL
within six bus CLK cycles, the master should
abort the transaction.
When DSCC4 is master, DEVSEL is input. If
DEVSEL is not activated within six clock
cycles after an address is output on AD(31:0),
the DSCC4 aborts the transaction and
generates an INTA.
When DSCC4 is slave, DEVSEL is output.
Note: DEVSEL is also valid in DEMUX mode.
Parity Error
When activated, indicates a parity error over
the AD(31:0) and C/BE(3:0) signals
(compared to the PAR input). It has a delay of
two CLK cycles with respect to AD and C/
BE(3:0) (i.e., it is valid for the cycle
immediately following the corresponding PAR
cycle).
PERR is asserted relative to the rising edge of
CLK.
34
for the configuration space registers.
Pin Descriptions
PEB 20534
PEF 20534
2000-05-30