peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 381

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

FE:
C:
BNO:
Frame
End
Descriptor
Pointer:
Data Sheet
Frame End
It indicates that the current receive data section (addressed by Receive
Data Pointer) contains the end of a frame (HDLC, PPP) or the end of data
block (ASYNC, BISYNC, XTRANS). This bit is set by the DMAC after
transferring the last data from the internal FIFO (indicated by the END bit)
into the receive data section. Moreover the BNO and STATUS is updated
and the ’C’ bit is set by the DMAC.
GMODE.CMODE=’0’:
After that it checks the HOLD bit stored in the on-chip memory. If
HOLD=’0’, it branches to the next receive descriptor. Otherwise the corre-
sponding DMAC receive channel is deactivated as long as the host CPU
does not request reactivation via the GCMDR register (action request with
’IDR’ command).
GMODE.CMODE=’1’:
After that it checks if the first (current) receive descriptor address (LRDA) is
equal to the last receive descriptor address (LRDA) stored in the
corresponding channel specific on-chip registers. When both addresses
differ, it branches to the next receive descriptor. Otherwise the
corresponding DMAC receive channel is deactivated as long as the host
CPU does not write a new LRDA value to LRDA register or provides an
action request with ’IDR’ command.
Complete
This bit is set by the DSCC4 if
- it completed filling data section normally
- it was aborted by a receiver reset command
- end of frame (HDLC, PPP) or end of block (ASYNC, BISYNC, BTRANS)
was stored in the receive data section.
Byte Number of Received Data
DSCC4 writes the number of data bytes it has stored in the current data
section into BNO
This 32-bit pointer is valid only in the descriptor, that contains the data
pointer to the first data section of an HDLC frame or ASYNC/BISYNC/
BTRANS block. This pointer is updated by the DSCC4 with the address of
the descriptor that contains the data pointer to the last section (FE) of the
HDLC frame or ASYNC/BISYNC/BTRANS block.
381
Host Memory Organization
PEB 20534
PEF 20534
2000-05-30