peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 187

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

PEB 20534
PEF 20534
Detailed Protocol Description
Receive direction:
The received CRC checksum is always assumed to be in the 2 (CRC-CCITT) or 4 (CRC-
32) last bytes of a frame, immediately preceding a closing flag. If bit ’RCRC’ is set, the
received CRC checksum is treated as data and will be written to the receive data buffer
in the shared memory where it precedes the frame status byte. Nevertheless the
received CRC checksum is additionally checked for correctness. If non-auto mode is
selected, the limits for ‘Valid Frame’ check are modified (refer to description of the
Receive Status Byte (RSTA)).
Transmit direction:
If bit ’XCRC’ is set, the CRC checksum is not generated internally. The checksum has to
be provided via the transmit data buffer by software. The transmitted frame will only be
closed automatically with a (closing) flag.
Note: The SCC does not check whether the length of the frame, i.e. the number of bytes,
to be transmitted makes sense or not according the HDLC protocol.
Data Sheet
187
2000-05-30