peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 286

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
BCR
TOE
SSEL
Bit Clock Rate
This bit is only valid in asynchronous PPP and ASYNC protocol mode
and only in clock modes not using the DPLL (0, 1, 3b, 7b). It is also
invalid in high speed operation clock mode 4.
BCR=’0’
BCR=’1’
Transmit Clock Out Enable
For clock modes 0b, 2b, 3a, 3b, 6b, 7a and 7b, the internal transmit clock
can be monitored on pin TxCLK as an output signal. In clock mode 5, a
time slot control signal marking the active transmit time slot is output on
pin TxCLK.
Bit ’TOE’ is invalid for all other clock modes.
TOE=’0’
TOE=’1’
Clock Source Select
Distinguishes between the ’a’ and ’b’ option of clock modes 0, 2, 3, 6 and
7.
SSEL=’0’
SSEL=’1’
Selects isochronous operation with bit clock rate 1. Data
bits are sampled once.
Selects standard asynchronous operation with bit clock
rate 16. Using 16 samples per bit, data bits are sampled 3
times around the nominal bit center. The resulting bit
value is determined by majority decision of the 3 samples.
For correct operation NRZ data encoding has to be
selected.
TxCLK pin is input.
TxCLK pin is switched to output function if applicable for
the selected clock mode.
Option ’a’ is selected.
Option ’b’ is selected.
286
Detailed Register Description
(async PPP, ASYNC modes)
PEB 20534
PEF 20534
(all modes)
(all modes)
2000-05-30