peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 67

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peb20534

Manufacturer Part Number
peb20534
Description
Dma Supported Serial Communication Controller With 4 Channels
Manufacturer
Infineon Technologies Corporation
Datasheet

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Table 12
DWORD
1
(read by
DMAC,
written by
CPU)
2
(read by
DMAC,
written by
CPU)
3
(read by
DMAC,
written by
CPU)
Data Sheet
FE
Hold
HI
NO
Next Tx Descr Ptr Next Transmit Descriptor Address:
Tx Data Buffer Ptr Transmit Data Buffer Start Address:
Bit Field
Transmit Descriptor Bit Field Description
Description
Frame End Indication:
Not evaluated by the DMAC. This bit indicates that this
descriptor contains a complete data packet or the last
part of a data packet. This indication is forwarded to the
corresponding SCC.
An ’FI’ interrupt is generated after completion of a
transmit descriptor with FE=’1’ setting.
Hold Indication:
Hold=’1’ marks the end of the descriptor chain. In this
case the DMAC will not branch to the next descriptor
address. The DMAC reads and evaluates Hold bit and
next descriptor address again on transmit poll request
command.(see
(this bit is ignored if DMAC is configured in last
descriptor address control mode)
Host Initiated Interrupt:
This bit set to ’1’ causes the DMAC to generate an
interrupt after completion of the descriptor and after
transfer of the complete data section from Host memory
to the central transmit FIFO. This may be used for
software control purposes.
Number OF Bytes:
This bit field determines the number of valid data bytes
in the transmit data buffer and the data buffer size. The
data buffer size is always n DWORDs, whereas n
depends on NO and the byte offset address ADD (refer
to ADD description on next pages).
The DMA Channel will branch to this address when
proceeding in the linked list.
The DMA Channel starts reading transmit data at this
address. Read access to transmit data buffer may
occur per single DWORD transfers or up to 15
DWORDs burst transfers.
67
Chapter
DMA Controller and Central FIFOs
5.1.2.3)
PEB 20534
PEF 20534
2000-05-30

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