peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 118

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

PEB 20534
PEF 20534
Multi Function Port (MFP)
When the transfer starts, the busy flag SSCBSY is set and a transmit interrupt request
(SSCTXI) will be generated to indicate that SSCTB may be reloaded again. When the
programmed number of bits (2 ... 16) has been transferred, the content of the shift
register is moved to the Receive Buffer SSCRB and a receive interrupt request
(SSCRXI) will be generated. If no further transfer is to take place (SSCTB is empty),
SSCBSY will be cleared at the same time. Software should not modify SSCBSY, as this
flag is hardware controlled.
Note that only one SSC can be master at a given time.
The transfer of serial data bits may be programmed in many respects:
• The data width may be selected in a range between 2 bits and 16 bits.
• Transfer may start with the LSB or the MSB.
• The shift clock may be idle low or idle high.
• Data bits may be shifted with the leading or trailing edge of the clock signal.
• The baudrate may be set from 152 Baud up to 5 MBaud (@ 20 MHz CPU clock).
• The shift clock can be either generated (master) or received (slave).
This flexible programming allows to adapt the SSC to a wide range of applications,
where serial data transfer is required.
The Data Width Selection allows to transfer frames of any length, from 2-bit ’characters’
up to 16-bit ’characters’. Starting with the LSB (SSCHB=’0’) allows communicating e.g.
with ASC0 devices in synchronous mode (C166 family) or 8051 like serial interfaces.
Starting with the MSB (SSCHB=’1’) allows to operate compatible with the SPI interface.
Regardless which data width is selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right aligned in registers SSCTB and SSCRB, with the
LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for
transfer by the internal shift register logic. The unselected bits of SSCTB are ignored, the
unselected bits of SSCRB will be not valid and should be ignored by the receiver service
routine.
The Clock Control allows to adapt transmit and receive behaviour of the SSC to a
variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out
transmit data, while the other clock edge is used to latch in receive data. Bit SSCPH
selects the leading edge or the trailing edge for each function. Bit SSCPO selects the
level of the clock line in the idle state. Hence for an idle-high clock the leading edge is a
falling one, a 1-to-0 transition. The figure below summarizes the clock control.
Data Sheet
118
2000-05-30