peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 263

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
RDR
RDT
IDR
IDT
Reset DMA Receiver (Channel i)
Self-clearing command bit.
This command resets the specific DMA controller receive channel. After
reset, the respective DMA channel is in its initial state equal to the reset
state after power on.
Reset DMA Transmitter (Channel i)
Self-clearing command bit.
This command resets the specific DMA controller transmit channel. After
reset, the respective DMA channel is in its initial state equal to the reset
state after power on.
Initialize DMA Receiver (Channel i)
Self-clearing command bit.
This command causes the specific DMA receive channel to fetch the
base descriptor address from register CHiBRDA and to branch to the
corresponding descriptor. Afterwards normal DMA operation on the
receive descriptor list is performed depending on the selected DMA
control mode.
Note: To avoid unexpected DMA controller behavior, it is recommended
Initialize DMA Transmitter (Channel i)
Self-clearing command bit.
This command causes the specific DMA transmit channel to fetch the
base descriptor address from register CHiBTDA and to branch to the
corresponding descriptor. Afterwards normal DMA operation on the
transmit descriptor list is performed depending on the selected DMA
control mode.
Note: To avoid unexpected DMA controller behavior, it is recommended
to apply ’IDR’ command only, if the specific DMA channel is in
reset state.
to apply ’IDT’ command only, if the specific DMA channel is in
reset state.
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Detailed Register Description
(RX Channel)
(RX Channel)
(TX Channel)
(TX Channel)
PEB 20534
PEF 20534
2000-05-30