peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 405

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

according to
the same time the next scan vector is loaded from TDI. Subsequently all output pins are
updated according to the new boundary scan contents and all input pins again capture
the current external level afterwards, and so on.
INTEST supports internal testing of the chip, i.e. the output pins capture the current level
on the corresponding internal line whereas all input pins are held on constant values (‘0’
or ‘1’, according to
The next test vector is serially loaded via TDI. Then all input pins are updated for the
following test cycle.
Note: In capture IR-state the code ‘001’ is automatically loaded into the instruction
SAMPLE/PRELOAD is a test mode which provides a snap-shot of pin levels during
normal operation.
IDCODE: A 32-bit identification register is serially read out via TDO. It contains the
version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits).
The LSB is fixed to ‘1’.
TDI ->
Note: Since in test logic reset state the code ‘011’ is automatically loaded into the
BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle.
Data Sheet
register, i.e. if INTEST is wanted the shift IR-state does not need to be passed.
instruction register, the ID code can easily be read out in shift DR state which is
reached by TMS = 0, 1, 0, 0.
Table
0011 0000 0000 0011 0110
108). Then the contents of the boundary scan is shifted to TDO. At
Table
108). The resulting boundary scan vector is shifted to TDO.
405
0000 1000 001
1
Test Configuration
-> TDO
PEB 20534
PEF 20534
2000-05-30