peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 245

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
ENDIAN
DBE
CMODE
Endian Selection
This bit selects whether receive and transmit data buffers are handled
with Intel or Motorola like byte ordering:
ENDIAN=’0’ The DWORDs of receive and transmit data buffers are
ENDIAN=’1’ The DWORDs of receive and transmit data buffers are
Note: The little/big endian selection (byte-swapping) effects only DSCC4
DEMUX Burst Enable
This bit is only valid if the DSCC4 is running in de-multiplexed bus
interface mode, i.e. pin DEMUX connected to V
By default value, the burst functionality is disabled in DEMUX mode and
can be enabled via setting this bit. However burst length is limited to 4
DWORDs in DEMUX mode (15 DWORDs in PCI mode):
DBE=’0’
DBE=’1’
DMA Control Mode
This bit selects between the two global DMA controller mechanisms for
handling descriptor chain end conditions:
CMODE=’0’ ’HOLD’ bit control mode.
CMODE=’1’ Last Receive/Transmit Descriptor Address mode.
operation on receive and transmit data buffer sections. Descriptor
reads and writes as well as register access is not effected anyway.
evaluated based on a little endian (Intel like) byte
ordering.
evaluated based on a big endian (Motorola like) byte
ordering. Therefore the byte ordering is automatically
swapped by the DMA controller.
Burst functionality is disabled. The DSCC4 will perform all
transactions to the host memory using single DWORD
read/write bus transfers.
Burst functionality is enabled. The DSCC4 performs burst
transfers for operation on descriptors and data sections
(like in PCI mode). Burst length is limited to 4 DWORDs
maximum.
The descriptor chain end condition is controlled via the
’HOLD’ bit in each receive/transmit descriptor.
The descriptor chain end condition is controlled via
registers LRDA/LTDA.
245
Detailed Register Description
DD3
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PEB 20534
PEF 20534
2000-05-30
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