peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 68

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 12
4
(written by
DMAC,
read by
CPU)
5
In detail the DMA controller reads a transmit buffer descriptor, calculates the data buffer
address and data buffer length and transfers data up to the burst size from the data
buffer into the central transmit FIFO. For a frame longer than the burst size, this
operation is repeated as long as the transmit FIFO requests for data. For more
information about FIFO control see
After the data buffer has been transferred, the controller marks the descriptor
“completed” and branches to the next descriptor if applicable. An ’FI’ interrupt will be
generated, if the currently completed descriptor contained an ’frame end/block end’
(FE=’1’) indication.
In HDLC mode data is transmitted as frames. The host indicates the end of a frame by
setting ’FE’ bit in the transmit descriptor. When a frame end is detected the DMA channel
forwards this information to the SCC. The SCC then terminates the transmission by
appending the CRC and the closing flag sequence to the data. If (FE=0 & HOLD=1) or
(FE=0 & FTDA=LTDA) an ERR interrupt is generated by the DMA controller (see
Chapter 5.1.2.3
Note: In contrast to HDLC mode all other modes (ASYNC, BISYNC, Extended
Although the DSCC4 works only DWORD oriented, it is possible to begin a transmit data
section at an uneven (not DWORD aligned) address. The two least significant bits (ADD)
of the transmit data pointer determine the beginning of the data section and the number
of data bytes in the first DWORD of the data section, respectively. Nevertheless the
DSCC4 will always perform DWORD read transfers (all byte enables valid) on transmit
data sections marking invalid bytes internally.
Data Sheet
Transparent Mode) are block/character oriented. Since the DMA controller does
not distinguish between different protocol modes (HDLC, ASYNC, ...) the ’FE’ bit
in the last descriptor of the linked list might be set also for the block/character
oriented modes as a kind of block end indication or together with an end of list
condition.
C
-
Transmit Descriptor Bit Field Description (cont’d)
and
Chapter
5.1.2.4).
Complete Bit:
This bit is set by the DMAC after having completed the
descriptor and corresponding data section.
The software can use this indication for memory and
linked list management.
Dummy DWORD;
Only necessary if compatibility between transmit and
receive descriptors is needed, i.e. receive descriptors
are manipulated by the host and attached to a transmit
descriptor list. For transmit operation, DWORD5 is
neither used by the DMAC nor by the host CPU.
Chapter
68
5.2.
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
2000-05-30