peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 330

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
RCE
RL(10:0)
Receive Length Check Enable
This bit is valid in HDLC mode only and enables/disables the receive
length check function:
RCE = ’0’
RCE = ’1’
Receive Length Check Limit
This bit-field defines the receive length check limit if checking is enabled
via bit ’RCE’:
RL(10:0)
No receive length check on received HDLC frames is
performed.
The receive length check is enabled. All bytes of a HDLC
frame which are transferred to the receive FIFO
(depending on the selected protocol sub-mode and
receive CRC handling) are counted and checked against
the maximum length check limit which is programmed in
bit field ’RL’.
A frame exceeding the maximum length is treated as if it
were aborted on the receive line (receive abort ’RAB’
interrupt and status indication).
In addition a ’FLEX’ interrupt is generated if enabled.
Note: The Receive Status Byte (RSTA) is part of the
The receive length limit is calculated by:
frame length checking.
Thus it is guaranteed, that the number of bytes
transferred to the host memory for one frame never
exceeds the value programmed to bit field ’RL’.
330
Limit
=
Detailed Register Description
RL
+
1
32
PEB 20534
PEF 20534
(hdlc mode)
(hdlc mode)
2000-05-30