peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 326

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
In operating modes that provide address recognition, the high/low byte of the received
address is compared with the individually programmable values in register RADR.
This addresses can be masked on a per bit basis by setting the corresponding bits in
register RAMR to allow extended broadcast address recognition. This feature is
applicable to all HDLC sub-modes with address recognition.
RAH1
RAL1
RAH2
RAL2
Receive Address 1 Byte High
In HDLC Automode bit ’1’ is reserved for ’CRI’ (Command Response
Indication). In all other modes RAH1 is an 8 bit address.
CRI
The setting of this bit effects the meaning of the ’C/R’ bit in the receive
status byte (RSTA):
C/R meaning
Command received
Response received
Note: If 1-byte address field is selected in HDLC Automode, RAH1 must
Receive Address 1 Byte Low
The general function whether it must be written or read by the CPU and
its meaning depends on the selected operating mode:
• Auto- / Non-Automode (16-bit address)
• Auto- / Non-Automode (8-bit address)
Receive Address 2 Byte High
Receive Address 2 Byte Low
Value of the second individually programmable high/low address byte. If
a 1-byte address field is selected, RAL2 is considered as the address of
a ’RESPONSE’ frame according to X.25 LAP-B protocol.
RAL1 can be programmed with the value of the first individual low
address byte.
According to X.25 LAP-B protocol, the address in RAL1 is considered
as the address of a ’COMMAND’ frame.
be set to 0x00
H
Command/Response Indication
.
326
C/R Value
0
1
CRI=1
Detailed Register Description
1
0
CRI=0
PEB 20534
PEF 20534
(hdlc mode)
(hdlc mode)
(hdlc mode)
(hdlc mode)
2000-05-30