peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 226

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 42
Data Sheet
22
21
20...16
15...10
9
8
7
6
5
4
3
2
1
0
0
00000
000000
FBBE
SERRE
0
PER
0
0
SC
BM
MS
B
B
B
B
B
Status and Command register bits (cont’d)
B
B
UDF Supported
No UDFs are supported by the DSCC4.
66 MHz Capable
The DSCC4 is not 66 MHz capable.
Reserved
Reserved
Fast Back-to-Back enable
A value of ’1’ means the DSCC4 is allowed to generate fast
Back-to-Back transactions to different agents.
A value of ’0’ means the DSCC4 is only allowed to generate
fast Back-to-Back transaction to the same agent.
SERR Enable
A value of ’1’ enables the SERR driver.
A value of ’0’ disables the SERR driver.
Wait Cycle Control
The DSCC4 does never perform address/data stepping.
Parity Error Response
When this bit is set the DSCC4 will take its normal action when
a parity error is detected. When this bit is ’0’ the DSCC4
ignores any parity errors that it detects and continues normal
operation.
VGA Palette Snoop
The DSCC4 is no VGA-Device.
Memory Write and Invalidate Enable
The “Invalidate” command is not supported by the DSCC4.
Special Cycles
All special cycles are ignored.
Note: Although this bit can be set it has no effect.
Bus Master
A value of ’1’ enables the bus master capability.
Note: Before giving the first action request it is necessary to
Memory Space
A value of ’1’ allows the DSCC4 to respond to Memory Space
Addresses.
Note: This bit must be set before the first read/write
set this bit.
transactions to the DSCC4 will be started.
226
Detailed Register Description
PEB 20534
PEF 20534
2000-05-30