peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 280

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
TEC
CEC
FCS
CTS
TIC Executing
TIC=’0’
TIC=’1’
Command Executing
CEC=’0’
CEC=’1’
Note: CEC will stay active if the SCC is in power-down mode or if no
Flow Control Status
If (in-band) flow control mechanism is enabled via bit ’FLON’ in register
CCR2 this bit indicates the current state of transmitter:
FCS=’0’
FCS=’1’
Clear To Send Input Signal State
CTS=’0’
CTS=’1’
Note: A transmit clock must be provided in order to detect the signal
serial clock, needed for command execution, is available.
state of the CTS pin.
Optionally this input can be programmed to generate an interrupt
on signal level changes.
No TIC (transmit immediate character) is currently in
transmission. Access to register TICR is allowed to initiate
a TIC transmission.
A TIC command (write access to register TICR) is
accepted but not completely executed. No further write
access to register TICR is allowed until ’TIC’ bit is cleared
by the DSCC4.
No command is currently in execution. The command
register CMDR can be written by CPU.
A command (written previously to register CMDR) is
currently in execution. No further command can be written
to register CMDR by CPU.
Transmitter is ready (always after transmitter reset
command or XON-character detected).
Transmitter is stopped (XOFF-character detected).
CTS input signal is inactive (high level)
CTS input signal is active (low level)
280
Detailed Register Description
(async mode)
(async mode)
PEB 20534
PEF 20534
(all modes)
(all modes)
2000-05-30