peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 430

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

13.6.5.3 Transmit Cycle Timing
Figure 101
Note:
1. Whichever supplies the transmit clock depending on the selected clock mode:
2. NRZ, NRZI and Manchester data encoding
3. FM0 and FM1 data encoding
4. If TxCLK output feature is enabled (only in some clock modes)
5. The timing is valid for non bus configuration modes and bus configuration mode 1. In
6. A transmit clock must be present to detect input level changes of signal CTS and to
Data Sheet
externally clocked via TxCLK, RxCLK or XTAL1 or
internally clocked via DPLL, BRG or BCR.
(No edge relation can be measured if the internal transmit clock is derived from the
external clock source by devision stages (BGR, BCR) or DPLL)
bus configuration mode 2, TxD and RTS are right shifted for 0.5 TxCLK periods i.e.
driven by the falling TxCLK edge.
change the output level of signal RTS.
Transmit Clock
(Note2,5)
(Note1)
(Note3)
(Note4)
(Note5)
TxCLK
CTS
RTS
CxD
TxD
TxD
Transmit Cycle Timing
101
102
103
106
430
104
100
102
103
105
Electrical Characteristics
PEB 20534
PEF 20534
106
2000-05-30