peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 81

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

5.1.3
The DSCC4 interrupt concept is based on 32-bit interrupt vectors generated by the
different blocks. Interrupt vectors are stored in a central interrupt FIFO which is 16
DWORDs deep. The interrupt controller transfers available vectors to one of ten circular
interrupt queues located in the shared memory depending on the source ID of each
interrupt vector.
In addition new interrupt vectors are indicated in the global status register GSTAR on a
per queue basis and selectively confirmed by writing ’1’ to the corresponding GSTAR bit
positions. The PCI interrupt signal INTA is asserted with any new interrupt event and
remains asserted until all events are confirmed.
Each interrupt queue length and memory location can be configured via specific interrupt
queue base address registers and two shared interrupt queue length registers. The
queue length is individually programmable in multiples of 32 DWORDs (see
One dedicated interrupt queue is provided per SCC channel and direction (IQSCCiRX
and IQSCCiTX). Non channel specific interrupt vectors generated by the DMAC itself are
transferred to the configuration queue IQCFG. The peripheral interrupt queue IQP is
used for vectors generated by one of the blocks GPP, SSC or LBI.
The internal blocks provide mask registers for suppressing interrupt indications. Masked
interrupts will neither generate an interrupt vector nor an INTA signal and GSTAR
indication. (Refer to figure
The DMA controller (interrupt controller) itself generates 6 channel specific interrupts
regarding the transmit and receive descriptor handling:
• Host Initiated interrupt (HI):
• Frame Indication interrupt (FI):
• Error interrupt (ERR):
Data Sheet
This interrupt can be forced by setting bit ’HI’ in the receive and transmit descriptor. In
this case the DMAC will generate an HI-interrupt with completion of this descriptor i.e.
when the DMAC is ready to branch to the next descriptor address. This might be used
to monitor the progress of the corresponding DMA channel on the descriptor list. As
an example the HI interrupt can be used to dynamically request attachment of new
receive descriptors to the list if the DMA channel comes close to the list end.
This interrupt is generated with completion of any receive and transmit descriptor with
a set ’frame end/block end’ indication, i.e. FE=’1’.
Indicates an unexpected descriptor configuration.
receive descriptor:
ERR is generated if receive data cannot be transferred to the shared memory
completely because the frame (block) does not fit into the current data section and a
HOLD condition (HOLD bit or LRDA=FRDA) prevents the DMAC from branching to
the next descriptor.
DMAC Interrupt Controller
“DSCC4 Logical Interrupt Structure” on Page
81
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
83.)
Page
2000-05-30
246).