peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 193

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

8.2.3
The selection of asynchronous or isochronous operation has no further influence on the
transmitter. The bit clock rate is solely a dividing factor for the selected clock source.
Transmission of the contents of the SCC transmit FIFO starts after providing data to the
DMA controller. The character frame for each character, consisting of start bit, the
character itself with defined character length, optionally generated parity bit and stop
bit(s) is assembled.
After finishing transmission (indicated by the ‘ALLS’ interrupt), IDLE sequence (logical
‘1’) is transmitted on transmit pin TxD.
Additionally, the CTS signal may be used to control data transmission.
8.2.4
8.2.4.1
Break generation:
On issuing the transmit break command (bit ’XBRK’ in register CCR2), the TxD pin is
immediately forced to physical ‘0’ level with the next following clock edge, and released
with the first clock edge after this command is reset again by software.
Break detection:
The SCC recognizes the break condition upon receiving consecutive (physical) ‘0’s for
the defined character length, the optional parity and the selected number of stop bits
(‘zero’ character and framing error). The ‘zero’ character is not pushed to RFIFO. If
enabled, the ’Break’ interrupt (BRK) is generated.
The break condition will be present until a ‘1’ is received which is indicated by the ‘Break
Terminated’ interrupt (BRKT).
8.2.4.2
Programmable XON and XOFF characters:
The XNXF register contains the programmable values for XON and XOFF characters.
The number of significant bits in a register is determined by the programmed character
length via bit field ’CHL’ in register CCR2.
Additionally, two programmable eight-bit values ’MXN’ and ’MXF’ serve as masks for the
characters XON and XOFF, respectively:
A ‘1’ in any mask bit position has the effect that no comparison is performed between the
corresponding bits in the received characters (‘don’t cares’) and the XON/XOFF value.
At RESET, the masks are ‘zero’ed, i.e. all bit positions will be compared.
A received character is considered to be recognized as a valid XON or XOFF character
Data Sheet
Data Transmission
Special Functions
Break Detection/Generation
In-band Flow Control by XON/XOFF Characters
193
Detailed Protocol Description
PEB 20534
PEF 20534
2000-05-30