peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 256

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
TFRTHRESi
(i = 0...3)
Mx_i
(i = 0...3)
Transmit FIFO Refill Threshold Channel i
These bit fields determine the channel specific Transmit FIFO Refill
Threshold for the corresponding channel i in number of DWORDs
multiplied by its respective multiplier Mx_i.
This threshold controls DMAC operation towards the Host memory.
A watermark is calculated by:
watermark = TFRTHRESH*Mx_i+1.
As soon as the number of valid data in the transmit FIFO is less than
watermark the DMA controller requests for new data from shared
memory.
After initialization the DMAC fills the complete transmit FIFO; when the
number of data in the transmit FIFO decreases below the watermark the
transmit FIFO requests for refill. The number of data to be transferred
into the transmit FIFO is calculated by:
number=TFSIZEi-watermark.
The transmit FIFO cannot be filled when the DMA channel is in internal
HOLD state, i.e. ’HOLD’ bit has been detected (GMODE.CMODE=’0’)
or Last Descriptor Address matches the current descriptor address
FTDA = LTDA (GMODE.CMODE=’1’).
Note: (1) The watermark has to be equal or lower than the specified size
Multiplier 2 or 4
These bits enable a multiplier 2 or 4 respectively for the corresponding
’TFRTHRESi’ value:
M2_i = ’0’
M2_i = ’1’
M4_i = ’0’
M4_i = ’1’
Note: It is recommended not to set both multiplier enable bits of one
of the corresponding central transmit FIFO partition.
(2) The refill watermark must be at least 2 DWORDs higher than
the forward watermark (refer also to register FIFOCR4).
(3) The minimum allowed TFRTHRESHi value for used channels
is “1”.
channel to ’1’.
The multiplier ’by 2’ is disabled
The ’TFRTHRESi’ bit field value is multiplied by 2.
The multiplier ’by 4’ is disabled
The ’TFRTHRESi’ bit field value is multiplied by 4.
256
Detailed Register Description
(TX Channel i)
(TX Channel i)
PEB 20534
PEF 20534
2000-05-30