peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 254

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 53
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
Bit 31
Bit 15
TFSIZEi
(i = 0...3)
30
14
TFSIZE0
TFSIZE3
FIFOCR1: FIFO Control Register 1
Transmit FIFO Size (Partition Channel i)
These bit fields determine the channel specific partition size of the
central transmit FIFO in multiples of 4 DWORDs:
partition size i = ’TFSIZEi’ * 4 DWORDs,
range 0...124 DWORDs
Note: The entire size of all FIFO partitions must not exceed the total
Note: If the complete central transmit FIFO is assigned to only one
Note: The minimum allowed partition size for used channels is 4
29
13
28
12
FIFO size of 128 DWORDs which is the responsibility of the
software.
channel, the maximum partition size is 124 DWORDs.
DWORDs, i.e. ’TFSIZEi’ = 1.
read/write
0000 0000
0044
written by CPU
evaluated by DSCC4
27
11
H
Central Transmit FIFO Partition Size
Central Transmit FIFO Partition Size
26
10
0
H
25
9
0
TFSIZE1
24
254
8
0
23
7
0
22
6
0
Detailed Register Description
21
5
0
20
4
0
TFSIZE2
19
3
0
(TX Channel i)
18
2
0
PEB 20534
PEF 20534
2000-05-30
17
1
0
16
0
0
0