NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 110

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

SRAM Overview
The mapping of a given access into the SRAM uses the following algorithm to determine
if the access hits in the memory:
if (RAMBAR[0] = 1)
4.3.2.2 SRAM Initialization
After a hardware reset, the contents of the SRAM module are undefined. The valid bit of
RAMBAR is cleared, disabling the module. If the SRAM needs to be initialized with
instructions or data, the following steps should be performed:
The ColdFire processor or an external BDM emulator using the debug module can perform
this initialization.
4-4
Bits
5–1
0
1. Load RAMBAR, mapping the SRAM module to the desired location.
2. Read the source data and write it to the SRAM. Various instructions support this
3. After data is loaded into the SRAM, it may be appropriate to load a revised value
function, including memory-to-memory MOVE instructions and the MOVEM
opcode. The MOVEM instruction is optimized to generate line-sized burst fetches
on 0-modulo-16 addresses, so this opcode generally provides the best performance.
into RAMBAR with new write-protect and address space mask attributes. These
attributes consist of the write-protect and address-space mask fields.
Name
SC,
UC,
C/I,
SD,
UD
if (requested address[31:12] = RAMBAR[31:12])
V
Address space masks (ASn). These fields allow certain types of accesses to be masked, or
inhibited from accessing the SRAM module. These bits are useful for power management as
described in Section 4.3.2.3, “Programming RAMBAR for Power Management.” In particular, C/I is
typically set.
The address space mask bits are follows:
C/I = CPU space/interrupt acknowledge cycle mask. Note that C/I must be set if BA = 0.
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each ASn bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. References to this address space cannot
Valid. Enables/disables the SRAM module. V is cleared at reset.
0 RAMBAR contents are not valid.
1 RAMBAR contents are valid.
access the SRAM module and are processed like other non-SRAM references.
Table 4-2. RAMBAR Field Description (Continued)
if (address space mask of the requested type = 0)
Access is mapped to the SRAM module
if (access = read)
if (access = write)
MCF5272 User’s Manual
Read the SRAM and return the data
if (RAMBAR[8] = 0)
else Signal a write-protect access error
Write the data into the SRAM
Description
MOTOROLA