NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 295

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
The most important considerations for PCB layout deal with noise: noise on the power
supply, noise generated by the digital circuitry on the device, and noise resulting from
coupling digital signals into the analog signals. The best PCB layout methods to prevent
noise–induced problems are as follows:
12.5.3 Recommended USB Protection Circuit
Figure 12-25 shows the recommended external ESD protection circuit for the USB.
• Keep digital signals as far away from analog signals (D+ and D-) as possible.
• Use short, low inductance traces for the analog circuitry to reduce inductive,
• Use short, low inductance traces for digital circuitry to reduce inductive, capacitive,
• Bypass capacitors should be connected between the Vdd and GND pairs with
• Use short, wide, low inductance traces to connect all of the GND pins together and,
• Use short, wide, low inductance traces to connect all of the Vdd power supply pins
• The 48-MHz oscillator must be located as close as possible to the chip package. This
capacitive, and radio frequency noise sensitivities.
and radio frequency radiated noise.
minimal trace length. These capacitors help supply the instantaneous currents of the
digital circuitry, in addition to decoupling the noise that may be generated by other
sections of the device or other circuitry on the power supply.
with a single trace, connect all of the GND pins to the power supply ground. This
helps to reduce voltage spikes in the ground circuit caused by high-speed digital
current spikes. Suppressing these voltage spikes on the integrated circuit is the
reason for multiple GND leads. A PCB with a ground plane connecting all of the
digital and analog GND pins together is the optimal ground configuration,
producing the lowest resistance and inductance in the ground circuit.
together and, with a single trace, connect all of the Vdd pins to the 3.3V power
supply. Connecting all of the digital and analog Vdd pins to the power plane would
be the optimal power distribution method for a multi-layer PCB with a power plane.
is required to minimize parasitic capacitance between crystal traces and ground.
Chapter 12. Universal Serial Bus (USB)
Line Interface
12-35