NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 546

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

SIM
Software watchdog timer, 6-12
SRAM
Stack pointer, 2-7, 2-7
Status register, 2-8
STOP instruction, 5-4, 5-16
Suggested reading, xlii
Supervisor
System configuration and protection, 1-5
System protection register, 6-6
T
TAP controller, 21-3
TCN0–TCN3, 15-5
Test access port, 1-7
Timer module
Timers
Timing
Index-8
overview, 1-5
programming model, 6-3
register memory map, 6-3
base address register, 4-3
initialization, 4-4
overview and operation, 4-2
programming model, 4-2
programming model, 2-8
capture registers, 15-5
counters, 15-5
event registers, 15-5
general-purpose registers, 15-3
mode registers, 15-3
operation, 15-2
overview, 1-7, 15-1
reference registers, 15-4
bus software watchdog, 20-25
branch instruction execution, 2-25
clock input and output, 23-5
fast Ethernet AC, 23-15
GPIO port AC, 23-25
JTAG AC, 23-26
MAC unit instructions, 3-5
MII
MII async input signal, 23-17
MOVE instructions, 2-20
one operand, 2-22
PLI, 23-20
processor bus input, 23-6
SDRAM interface, 23-13
serial management channel, 23-17
timer module AC, 23-18
two operands, 2-23
USART AC, 23-19
USB interface AC, 23-25
transmit signal, 23-16
MCF5272 User’s Manual
INDEX
Timings
Transmit signal timing, 23-16
U
UART modules
USB
SDRAM refresh, 9-20
bus operation
clock source baud rates, 16-21
external clock, 16-22
FIFO stack in UART0, 16-26
initialization sequence, 16-32
looping modes, 16-28
mode registers, 16-5
multidrop mode, 16-29
overview, 1-6
programming, 16-31
receiver enabled, 16-25
register description, 16-3
serial overview, 16-2
signal definitions, 16-19
transmitter/receiver
transmitting in UART mode, 16-23
access times, 12-28
alternate settings register, 12-11
architecture, 12-3
attachment detection, 12-34
buffer descriptors, 11-32
class- and vendor-specific request operation, 12-32
clock generator, 12-4
configuration and interface changes, 12-29
configuration RAM, 12-26, 12-28
control logic, 12-4
control, bulk, and interrupt endpoints, 12-30
data flow, 12-30
device configuration example, 12-27
endpoint
endpoint control registers, 12-16, 12-19
FIFO configuration, 12-29
interrupt acknowledge cycles, 16-31
read cycles, 16-31
write cycles, 16-31
automatic echo, 16-28
local loop-back, 16-28
remote loop-back, 16-29
clock source, 16-20
modes, 16-23
controllers, 12-5
data present registers, 12-25
data registers, 12-25
FIFOs, 12-28
halt feature, 12-33
interrupt mask registers, 12-24
status interrupt registers, 12-23
MOTOROLA