NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 311

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
13.5 PLIC Registers
Any bits in the following registers marked 0 have no function. When the register is a
read/write register, these bits should be cleared.
Some registers are described that control more than one port. In these cases, parentheses
indicates to which port the control bits relate; for example, LM0(0) is the LM0 bit for
port 0.
13.5.1 B1 Data Receive Registers (P0B1RR–P3B1RR)
All bits in these registers are read only and are set on hardware or software reset.
The PnB1RRs contain the last four frames of data received on channel B1. (P0B1RR is the
B1 channel data for port 0, P1B1RR is B1 for port 1, and so on.) The data are packed from
the least significant byte (LSB), up to the most significant byte (MSB).
These registers are aligned on longword boundaries from MBAR + 0x300 for P0B1RR to
MBAR + 0x30C for P3B1RR. See Section 13.2.3, “GCI/IDL B- and D-Channel Bit
Alignment,” for the frame and bit alignment within the 32-bit word.
0x0394
0x0398
0x039C
0x036C
0x037C
0x038C
0x0370
0x0374
0x0378
0x0383
0x0384
0x0388
0x0390
MBAR
Offset
Port0 GCI C/I Rx
Port0 GCI C/I Tx
Aperiodic Interrupt status register (PASR)
(P0GCIR)
Reserved
(P0GCIT)
[31:24]
Port2 GCI monitor Tx (P2GMT)
Port0 periodic status (P0PSR)
Port2 periodic status (P2PSR)
Table 13-1. PLIC Module Memory Map (Continued)
Port0 Sync Delay (P0SDR)
Port2 Sync Delay (P2SDR)
Chapter 13. Physical Layer Interface Controller (PLIC)
Reserved
Reserved
GCI monitor Tx status
Port1 GCI C/I Rx
Port1 GCI C/I Tx
(P1GCIR)
(PGMTS)
(P1GCIT)
Reserved
Reserved
[23:16]
GCI monitor Tx abort
Port2 GCI C/I Rx
Port2 GCI C/I Tx
(P2GCIR)
(P2GCIT)
Reserved
(PGMTA)
[15:8]
Port3 GCI monitor Tx (P3GMT)
Port1 periodic status (P1PSR)
Port3 periodic status (P3PSR)
D-Channel Request (PDRQR)
Port1 Sync Delay (P1SDR)
Port3 Sync Delay (P3SDR)
Clock Select (PCSR)
GCI C/I D-Channel
Loop back Control
GCI C/I Tx Status
Port3 GCI C/I Rx
Port3 GCI C/I Tx
Status (PDCSR)
(PGCITSR)
Reserved
(P3GCIR)
(P3GCIT)
PLIC Registers
(PLCR)
[7:0]
13-15