NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 319

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
PnPSR are 16-bit registers containing the interrupt status information for the B- and
D-channel transmit and receive registers for each of the four ports on the MCF5272.
15–12
Bits
11
10
9
8
7
6
5
4
3
2
1
0
B2ROE
B1ROE
B2RDF
B1RDF
B2TUE
B1TUE
B2TDE
B1TDE
DROE
Name
DTUE
DTDE
DRDF
—
Reserved, should be cleared.
D data transmit underrun error. This bit is set when the data in the PLTD transmit data
register for the respective port was transferred to the transmit shadow register, which was
already empty indicated by DTDE. DTUE is automatically cleared, when the PnPSR
register has been read by the CPU.
B2 data transmit underrun error. This bit is set when the data in the PnB2TR transmit data
register for the respective port was transferred to the transmit shadow register, which was
already empty indicated by B2TDE. B2TUE is automatically cleared when the PnPSR
register has been read by the CPU.
B1 data transmit underrun error. This bit is set when the data in the PnB1TR transmit data
register for the respective port was transferred to the transmit shadow register, which was
already empty indicated by B1TDE. B1TUE is automatically cleared when the PnPSR
register has been read by the CPU.
D-Channel data receive overrun error. This bit is set when the data in the D receive
shadow register for the respective port has been transferred to the receive data register
PnDRR, which was already full indicated by DRDF. DROE is automatically cleared when
the PnPSR register has been read by the CPU.
B2 data receive overrun error. This bit is set when the data in the B2 receive shadow
register for the respective port has been transferred to the receive data register PnB2RR,
which was already full indicated by B2RDF. B2ROE is automatically cleared when the
PnPSR register has been read by the CPU.
B1 data receive overrun error. This bit is set when the data in the B1 receive shadow
register for the respective port has been transferred to the receive data register PnB1RR,
which was already full indicated by B1RDF. B1ROE is automatically cleared when the
PnPSR register has been read by the CPU. Note: Overrun and Underrun conditions are
caused by the B and/or D-channel receive or transmit data registers not being read or
written prior to a 2-KHz super frame arriving.
D data transmit data empty. This bit is set when the data in the PLTD transmit data register
for the respective port has been transferred to the transmit shadow register. This bit is
cleared when the CPU writes data to PLTD.
B2 data transmit data empty. This bit is set when the data in the PnB2TR transmit data
register for the respective port has been transferred to the transmit shadow register. This
bit is cleared when the CPU writes data to PnB2TR.
B1 data transmit data empty. This bit is set when the data in the PnB1TR transmit data
register for the respective port has been transferred to the transmit shadow register. This
bit is cleared when the CPU writes data to PnB1TR.
D receive data full. This bit indicates that the D receive data register for the respective port
is full. DRDF is cleared when the CPU reads the receive data register PnDRR.
B2 receive data full. This bit indicates that the B2 receive data register for the respective
port is full. B2RDF is cleared when the CPU reads the receive data register PnB2RR.
B1 receive data full. This bit indicates that the B1 receive data register for the respective
port is full. B1RDF is cleared when the CPU reads the receive data register PnB2RR.
Chapter 13. Physical Layer Interface Controller (PLIC)
Table 13-5. P0PSR–P3PSR Field Descriptions
Description
PLIC Registers
13-23