NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 203

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
9.6 Auto Initialization
Each SDRAM requires an initialization sequence before it can be accessed. After power up,
the SDRAM requires a certain time (100 µS) before it can accept the first command of the
initialization procedure. After this time, one
commands are required. After initialization, an
executed, which writes the SDRAM configuration into the SDRAM device mode register.
SDRAM mode register data is transferred on the address signals, so all SDRAM devices
are configured simultaneously.
Initialization is enabled by setting SDCR[INIT] and performing a dummy write to the
SDRAM address space. The SDRAM controller executes the required
REFRESH
SDRAM as follows:
SDCR[ACT] is set after initialization.
9.7 Power-Down and Self-Refresh
The SDRAM can be powered down by setting SDCR[GSL]. The SDRAM controller
executes the required power-down command sequence to ensure self-refresh during power
down. The SDRAM controller completes the current memory access then automatically
issues the following commands to force the SDRAM into sleep mode:
PRECHARGE ALL BANKS
NOP
AUTO REFRESH COMMAND
Bits
3–2
1–0
• SDRAM internal burst is always disabled.
• CAS latency is defined by SDTR[CLT].
Name
RCD
CLT
commands and automatically loads the mode register, which configures the
RAS-to-CAS delay. The reset value is 1, requiring 2 clock cycles for SDRAM activation.
00 1 cycle
01 2 cycles (default)
10 3 cycles
11 4 cycles
CAS latency. Specifies the delay programmed into the SDRAM mode register during initialization,
indicating the time between a
the pins. The SDRAM controller uses this value to sequence its state machine during read
operations. CLT cannot be changed after the mode register is written.
00 Reserved
01 2-cycle CAS latency (default)
1x Reserved
Table 9-8. SDTR Field Descriptions (Continued)
Chapter 9. SDRAM Controller
READ
command being issued to the SDRAM and data appearing on
PRECHARGE ALL
Description
INITIATE LOAD REGISTER SET
command and eight
PRECHARGE
Auto Initialization
command is
REFRESH
and
9-9