NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 327

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
13.5.20 D-Channel Request Register (PDRQR)
All bits in this read/write register are cleared on hardware or software reset.
The PDRQR register contains D-channel control bits for all four ports on the MCF5272.
Reset
Field
Addr
R/W
15–12
Bits
11, 9
10, 8
Bits
7–2
1–0
4
3
2
1
0
15
Name
DG0
DC3
DC2
DC1
DC0
—
DCNTI
Name
SHDD
DRQ
—
—
Figure 13-32. D-Channel Request Registers (PDRQR)
12
D-channel grant, port 0. See DG1.
D-channel change, port 3.
0 Default reset value.
1 Indicates that a value other than 0xFF (all ones) exists the D-channel receive register.
D-channel change, port 2. See DC3.
D-channel change, port 1. See DC3.
D-channel change, port 0. See DC3.
Chapter 13. Physical Layer Interface Controller (PLIC)
Reserved, should be cleared.
D-channel shift direction.
0 D-channel data is msb first. The first bit received is assumed to be the most
1 D-channel data is lsb first for the D channel. The first bit received is assumed to be
D-channel control ignore. Allows the D-Channel contention function to be ignored.
Reserved, should be cleared.
The value written to these bits is driven onto the DREQ pins associated with port 0
and port 1. When set, a logic high, 1, is driven on to the corresponding pin.
SHDD(1) DCNTI(1) SHDD(0) DCNTI(0)
significant bit and is loaded into the msb position of the D-channel receive register
for the respective port. SHDD(1) configures the shift direction for ports 1, 2 and 3,
SHDD(0) configures the shift direction for port 0.
the least significant bit and is loaded into the lsb position of the D-channel receive
register for the respective port.
Table 13-15. PDRQR Field Descriptions
Table 13-14. PDCSR Field Descriptions
00 contention active on both ports
01 ignore contention on port 0
10 ignore contention on port 1
11 ignore contention on both ports
11
10
0000_0000_0000_0000
MBAR + 0x392
9
Read/Write
Description
Description
8
7
—
2
PLIC Registers
1
DRQ
13-31
0