NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 62
![KIT DEVELOP NETWORK FOR MOD5272](/photos/9/6/90647/nndk-mod5272-kit_sml.jpg)
NNDK-MOD5272-KIT
Manufacturer Part Number
NNDK-MOD5272-KIT
Description
KIT DEVELOP NETWORK FOR MOD5272
Manufacturer
NetBurner Inc
Series
ColdFire®r
Datasheets
1.MOD5272-100IR.pdf
(2 pages)
2.MOD5272-100IR.pdf
(550 pages)
3.NNDK-MOD5282-KIT.pdf
(2 pages)
Specifications of NNDK-MOD5272-KIT
Main Purpose
*
Embedded
*
Utilized Ic / Part
MOD5272
Primary Attributes
*
Secondary Attributes
*
Processor To Be Evaluated
MOD5272
Interface Type
RS-232, RS-485, USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
528-1001
- Current page: 62 of 550
- Download datasheet (6Mb)
MCF5272 Architecture
1.2 MCF5272 Architecture
This section briefly describes the MCF5272 core, SIM, UART, and timer modules, and test
access port.
1.2.1 Version 2 ColdFire Core
Based on the concept of variable-length RISC technology, ColdFire combines the
simplicity of conventional 32-bit RISC architectures with a memory-saving,
variable-length instruction set. The main features of the MCF5272 core are as follows:
1-4
• System integration module (SIM)
• Physical layer interface controller (PLIC)
• IEEE 1149.1 boundary-scan test access port (JTAG) for board-level testing
• Operating voltage: 3.3 V ±0.3 V
• Operating temperature: 0 ° –70 ° C
• Operating frequency: DC to 66 MHz, from external CMOS oscillator
• Compact ultra low-profile 196 ball-molded plastic ball-grid array package (PGBA)
• 32-bit address bus directly addresses up to 4 Gbytes of address space
• 32-bit data bus
• Variable-length RISC
• Optimized instruction set for high-level language constructs
• Sixteen general-purpose 32-bit data and address registers
• MAC unit for DSP applications
• Supervisor/user modes for system protection
• Vector base register to relocate exception-vector table
• Special core interfacing signals for integrated memories
• Full debug support
— System configuration including internal and external address mapping
— System protection by hardware watchdog
— Versatile programmable chip select signals with wait state generation logic
— Up to three 16-bit parallel input/output ports
— Latchable interrupt inputs with programmable priority and edge triggering
— Programmable interrupt vectors for on-chip peripherals
— Allows connection using general circuit interface (GCI) or interchip digital link
— Three physical interfaces
— Four time-division multiplex (TDM) ports
(IDL) physical layer protocols for 2B + D data
MCF5272 User’s Manual
MOTOROLA
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