NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 7

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
4.1
4.2
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.4
4.4.1
4.4.2
4.4.2.1
4.4.2.2
4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.2.3
4.5.2.3.1
4.5.2.3.2
4.5.2.4
4.5.2.5
4.5.3
4.5.3.1
4.5.3.2
5.1
5.2
5.3
5.3.1
5.4
5.4.1
5.4.2
5.4.3
5.4.4
Paragraph
Number
Interactions between Local Memory Modules ................................................... 4-1
Local Memory Registers..................................................................................... 4-2
SRAM Overview ................................................................................................ 4-2
ROM Overview................................................................................................... 4-5
Instruction Cache Overview ............................................................................... 4-7
Overview............................................................................................................. 5-1
Signal Description............................................................................................... 5-2
Real-Time Trace Support.................................................................................... 5-2
Programming Model ........................................................................................... 5-5
SRAM Operation ............................................................................................ 4-2
SRAM Programming Model........................................................................... 4-2
ROM Operation .............................................................................................. 4-5
ROM Programming Model............................................................................. 4-6
Instruction Cache Physical Organization........................................................ 4-7
Instruction Cache Operation ........................................................................... 4-9
Instruction Cache Programming Model........................................................ 4-12
Begin Execution of Taken Branch (PST = 0x5) ............................................. 5-4
Revision A Shared Debug Resources ............................................................. 5-7
Address Attribute Trigger Register (AATR) .................................................. 5-7
Address Breakpoint Registers (ABLR, ABHR) ............................................. 5-8
Configuration/Status Register (CSR).............................................................. 5-9
SRAM Base Address Register (RAMBAR)............................................... 4-3
SRAM Initialization.................................................................................... 4-4
Programming RAMBAR for Power Management ..................................... 4-5
ROM Base Address Register (ROMBAR) ................................................. 4-6
Programming ROMBAR for Power Management ..................................... 4-7
Interaction with Other Modules.................................................................. 4-9
Cache Coherency and Invalidation ............................................................. 4-9
Caching Modes ........................................................................................... 4-9
Reset ......................................................................................................... 4-11
Cache Miss Fetch Algorithm/Line Fills ................................................... 4-11
Cache Control Register (CACR) .............................................................. 4-13
Access Control Registers (ACR0 and ACR1) .......................................... 4-15
Cacheable Accesses .............................................................................. 4-10
Cache-Inhibited Accesses..................................................................... 4-10
CONTENTS
Debug Support
Local Memory
Chapter 4
Chapter 5
Contents
Title
Number
Page
vii