NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 243

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
The MII_SPEED field must be programmed with a value to provide an E_MDC frequency
of less than or equal to 2.5 MHz to be compliant with the IEEE MII specification. The
MII_SPEED must be set to a non-zero value in order to source a read or write management
frame. After the management frame is complete, the MSCR register may optionally be set
to zero to turn off the E_MDC. The E_MDC generated will have a 50% duty cycle except
when MII_SPEED is changed during operation. Change will take effect following either a
rising or falling edge of E_MDC.
If the system clock is 50 MHz, programming this register to 0x0000_000A results in an
E_MDC frequency of 25 MHz * 1/10 = 2.5 MHz. Table 11-15 shows optimum values for
MII_SPEED as a function of system clock frequency.
11.5.9 FIFO Receive Bound Register (FRBR)
FRBR is a read-only register used to determine the upper address boundary of the FIFO
RAM. Drivers can use this value, along with the registers FRSR and TFSR, to appropriately
divide the available FIFO RAM between the transmit and receive data paths. The value in
this register must be added to MBAR + 0x800 to determine the absolute address.
31–8
Bits
6–1
7
0
DIS_PREAMBLE
MII_SPEED
System Clock Frequency
Name
—
—
Table 11-15. Programming Examples for MSCR Register
25 MHz
33 MHz
50 MHz
66 MHz
Reserved, should be cleared.
Disable preamble. Asserting this bit causes the preamble of 32 consecutive 1’s not to
be prepended to the MII management frame. The MII standard allows the preamble
to be dropped if the attached PHY device(s) do not require it.
MII frequency divider. MII_SPEED controls the frequency of the MII management
interface clock (E_MDC) relative to system clock. A value of 0 in this field turns off the
E_MDC and leaves it in low-voltage state. Any non-zero value results in an E_MDC
frequency given by the following formula:
MDC_FREQUENCY = system frequency / (4 * MII_SPEED)
Reserved, should be cleared.
Table 11-14. MSCR Field Descriptions
Chapter 11. Ethernet Module
[MII_SPEED]
0x3
0x4
0x5
0x7
Description
E_MDC frequency
2.08 MHz
2.06 MHz
2.36 MHz
2.5 MHz
Programming Model
11-19