NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 79

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
2.4.1 Organization of Integer Data Formats in Registers
Figure 2-7 shows the integer format for data registers. Each integer data register is 32 bits
wide. Byte and word operands occupy the lower 8- and 16-bit portions of integer data
registers, respectively. Longword operands occupy the entire 32 bits of integer data
registers. A data register that is either a source or destination operand only uses or changes
the appropriate lower 8 or 16 bits in byte or word operations, respectively. The remaining
high-order portion does not change. The least significant bit (lsb) of all integer sizes is zero,
the most-significant bit (msb) of a longword integer is 31, the msb of a word integer is 15,
and the msb of a byte integer is 7.
The instruction set encodings do not allow the use of address registers for byte-sized
operands. When an address register is a source operand, either the low-order word or the
entire longword operand is used, depending on the operation size. Word-length source
operands are sign-extended to 32 bits and then used in the operation with an address register
destination. When an address register is a destination, the entire register is affected,
regardless of the operation size. Figure 2-8 shows integer formats for address registers.
The size of control registers varies according to function. Some have undefined bits
reserved for future definition by Motorola. Those particular bits read as zeros and must be
written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations. For all CCR operations, the
upper byte is read as all zeros and is ignored when written, regardless of privilege mode.
Figure 2-8. Organization of Integer Data Formats in Address Registers
msb
msb
31
31
31
31
31
31
30
30
Figure 2-7. Organization of Integer Data Formats in Data Registers
Not used
Not used
Sign-Extended
Longword
16
Chapter 2. ColdFire Core
msb
Full 32-Bit Address Operand
15
8
msb Low order byte
14
7
Lower order word
6
16
15
1
1
1
1
16-Bit Address Operand
lsb
lsb
lsb
lsb
0
0
0
0
Organization of Data in Registers
Bit (0 ≤ bit number ≤ 31)
Byte (8 bits)
Word (16 bits)
Longword (32 bits)
0
0
2-11