NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 170

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

Programming Model
6.2.4 System Protection Register (SPR)
The system protection register (SPR), Figure 6-4, provides information about bus cycles
that have generated error conditions. These error conditions can optionally generate an
access error exception by using the enable bits.
6-6
Bits
5–4
2–0
8
7
6
3
SoftRST
BusLock Locks the ownership of the bus.
Priority
Address
Field
HWR
AR
—
Reset
Reset
Field
Field ADCEN
R/W
R/W
Selects the bus arbiter priority scheme.
0 Ethernet has highest priority, DMA has next highest priority, CPU has lowest priority.
1 CPU has highest priority, DMA has next highest priority, Ethernet has lowest priority.
This bit should be cleared if the Ethernet module is enabled.
Assume request. Selects the bus mastership scheme.
0 Current bus master relinquishes the bus after the current bus cycle.
1 Assume current bus master wants the bus for the next bus cycle and include it in the arbitration
Writing a one to this bit resets the on-chip peripherals, excluding the chip select module, interrupt
controller module, GPIO module, and SDRAM controller, and asserts RSTO. The CPU is not
reset. The reset remains asserted for 128 clock cycles. This bit is automatically cleared on
negation of the reset.
Reserved, should be cleared.
0 Ownership of the bus is determined by arbitration.
1 Current bus master retains ownership of the bus indefinitely.
Hardware watchdog reference. Determines how many clocks to wait before timing out a bus
cycle when SPR[HWTEN] is set. The value programmed should be longer than the response
time of the slowest external peripheral in the system.
000 128
001 256
010 512
011 1024
100 2048
101 4096
110 8192
111 16384
process. If AR is set and the current bus master has a higher priority than other requesting
masters but is not requesting the bus for the next cycle, there is a 1 clock dead cycle before the
arbiter can reassign the bus to the next highest priority master.
ADC
15
7
Table 6-3. SCR Field Descriptions (Continued)
Figure 6-4. System Protection Register (SPR)
WPVEN
WPV
14
6
SMVEN
SMV
MCF5272 User’s Manual
13
5
PEEN
MBAR + 0x006
PE
12
4
0000_0000
0000_1011
R/W
R/W
Description
HWTEN
HWT
11
3
RPVEN
RPV
10
2
EXTEN
EXT
9
1
SUVEN
SUV
8
0
MOTOROLA