NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 78
NNDK-MOD5272-KIT
Manufacturer Part Number
NNDK-MOD5272-KIT
Description
KIT DEVELOP NETWORK FOR MOD5272
Manufacturer
NetBurner Inc
Series
ColdFire®r
Datasheets
1.MOD5272-100IR.pdf
(2 pages)
2.MOD5272-100IR.pdf
(550 pages)
3.NNDK-MOD5282-KIT.pdf
(2 pages)
Specifications of NNDK-MOD5272-KIT
Main Purpose
*
Embedded
*
Utilized Ic / Part
MOD5272
Primary Attributes
*
Secondary Attributes
*
Processor To Be Evaluated
MOD5272
Interface Type
RS-232, RS-485, USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
528-1001
- Current page: 78 of 550
- Download datasheet (6Mb)
Integer Data Formats
2.2.2.4 Access Control Registers (ACR0–ACR1)
The access control registers (ACR0–ACR1) define attributes for two user-defined memory
regions. Attributes include definition of cache mode, write protect and buffer write enables.
See Section 4.5.3.2, “Access Control Registers (ACR0 and ACR1).”
2.2.2.5 ROM Base Address Register (ROMBAR)
The ROMBAR base address register determines the base address of the internal ROM
module and indicates the types of references mapped to it. The ROMBAR includes a base
address, write-protect bit, address space mask bits, and an enable. Note that the MCF5272
ROM contains data for the HDLC module and is not user programmable. See
Section 4.4.2.1, “ROM Base Address Register (ROMBAR).”
2.2.2.6 RAM Base Address Register (RAMBAR)
The RAMBAR register determines the base address location of the internal SRAM module
and indicates the types of references mapped to it. The RAMBAR includes a base address,
write-protect bit, address space mask bits, and an enable. The RAM base address must be
aligned on a 0-modulo-4-Kbyte boundary. See Section 4.3.2.1, “SRAM Base Address
Register (RAMBAR).”
2.2.2.7 Module Base Address Register (MBAR)
The module base address register (MBAR) defines the logical base address for the
memory-mapped space containing the control registers for the on-chip peripherals. See
Section 6.2.2, “Module Base Address Register (MBAR).”
2.3 Integer Data Formats
Table 2-4 lists the integer operand data formats. Integer operands can reside in registers,
memory, or instructions. The operand size for each instruction is either explicitly encoded
in the instruction or implicitly defined by the instruction operation.
2.4 Organization of Data in Registers
The following sections describe data organization within the data, address, and control
registers.
2-10
Table 2-4. Integer Data Formats
Bit
Byte integer
Word integer
Longword integer
Operand Data Format
MCF5272 User’s Manual
16 bits
32 bits
8 bits
Size
1 bit
MOTOROLA
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